Field of the Invention
The present invention relates to a formation method of forming, on a substrate, a fin pattern in which a plurality of fins are arrayed.
Description of the Related Art
The miniaturization of a transistor is required as the microfabrication of a circuit pattern of a semiconductor integrated circuit rises. However, if a gate length is shortened in order to achieve the miniaturization of the transistor, a drain leakage current may increase due to a short channel effect. To cope with this, there has been proposed a fin transistor which reduces the drain leakage current by a structure in which a channel portion is formed into a fin shape and the channel portion is sandwiched by a gate electrode. In a CMOS circuit using such a fin transistor, for example, a plurality of linear fins are formed on a substrate including an n-type active region and a p-type active region adjacent to each other, and a gate electrode common to the plurality of fins is provided (see U.S. Patent Application Publication No. 2010/287518).
In the fin formed at the boundary of the n-type active region and the p-type active region, a desired characteristic cannot be obtained when the fin is operated as the transistor. Therefore, the fin is not preferably formed at the boundary. In this case, it is desirable to fabricate a process of forming the plurality of fins on the substrate so as not to form the fin at the boundary of the n-type active region and the p-type active region.